The new CDC 3231G-Cx is a pin-compatible mask ROM derivative of Micronas’ 32-bit Car Dashboard Controller family based on an ARM7TDMI^TM CPU core (CDC 32xxG).

This device comes along with additional features of the Cx platform like a superior power saving module (PSM), one high-speed CAN module (Bosch V2.0B), and an optional device lock module to inhibit Flash access. Main characteristics of the PSM are three additional low-power modes (IDLE, WAKE, and STANDBY), an internal RC oscillator, a polling/Flash timer output, as well as an RTC (Real Time Clock). The CDC 3231G also contains the patented built-in ERM (EMI Reduction Module).

System Architecture

The internal high-speed bus connects the following peripherals to the ARM7TDMI processor:

ICU (Interrupt Control Unit)

SRAM

The 16/32-bit bus connects to the mask ROM. All other peripherals are connected to the I/O bus. All I/O ports have multiple functions to obtain utmost flexibility. A total of 91 GPIOs can be selected.

The built-in ERM delivers superb EMI results reducing the peak values by up to 10 dBμV.

The CDC 3231G is fully pin- and software-compatible with all other members of the CDC 32xxG family.

Block diagram of the CDC 3231G

Main Features

128 KB mask ROM

6 KB SRAM

Four CPU operation modes (Deep Slow, Slow, Fast, PLL)

Three low-power modes (Idle, Wake, Standby)

RTC delivering hours, minutes, seconds

Polling/Flash timer output

PLL circuitry delivering up to 50 MHz

4- to 5-MHz oscillator

EMI reduction module (ERM)

Digital watchdog

Central clock divider

Interrupt controller with 26 inputs and 16 priority levels

Five port interrupts

Regulator input supervision for reset/alarm (alarm comparator)

Clock and supply supervision

16-channel 10-bit ADC

Two comparators

ADC reference (1 internal, 3 external)

46×4 LCD module

One UART, two SPIs

DigitBus master module

One CAN module with 512 Bytes of object RAM according to Bosch specification V2.0B (32 message objects)

One I2C master module

Four stepper motor drivers

Five PWM modules (configurable as 2×8 bit or 1×16 bit)

Sound generator with auto decay

Two SW-selectable clock outputs

16-bit free-running counter with four capture/compare modules

1×16-bit timer and 4×8-bit timer

Patch module (up to 10 cells)

JTAG interface

-40 to +105 °C case temperature range

Single 3.5 V to 5.5 V supply voltage (limited I/O performance below 4.5 V)

Up to 91 GPIOs

128 pin PQFP package, 0.5 mm pin pitch

Development Tools

Evaluation chip CDC 3205G featuring

ETM via embedded emulation JTAG

ROM/Flash emulation with external SRAM (up to 8 MBytes)

Evaluation Board (EVB) including the CDC 3205G for evaluation and debugging of embedded systems

Application Board (APB) for Flash memory programming

Probe for PQFP128

Software environment (compiler, linker, assembler) from 3rd party vendors

RTOS from 3rd party vendors

CAN protocol stacks

Development tool setup