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Short description
Block diagram
Features
Short description

The DPS 9455B is a single-chip digital display processor and scaler, especially designed for FPD-TV sets (LCD-TV, PDP-TV) supporting HDTV signal input and de-interlacing as well as PC-signal input. The DPS 9455B is a new member of Micronas’ IC family implemented in deep submicron CMOS technology.

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Block diagram

System Architecture

The block diagram shows the DPS 9455B. The device has digital outputs. In principle, the device comprises three major functional and clock domain parts.

The functional parts are

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Video input processing,
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Scaling, and
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Display processing.

The clock domains are

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ITU domain,
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Input domain, and
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Display domain (compare the block diagram and the different shaded areas).

The input and the output signals of the IC can be chosen in various configurations.

Block diagram of the DPS 9455B
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Features

Video Inputs

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Digital input for 50/60 I or 50/60 P signals in ITU-656 (8 bit) or ITU-601 (16 bit)
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3×8 bit YCrCb/RGB input
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2 analog RGB/YCrCb inputs for Teletext, graphics, 480p, 576p, 1080i and 720p
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4 built-in ADCs (8-bit) for RGB + Fast-Blank with 81 MHz sampling rate
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PC input up to XGA at 75 Hz and WXGA at 60 Hz
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Separate HS and VS (2×) inputs

Sync Processing

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3-level sync-separation for 1080i and 720p
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HS and VS outputs to synchronize
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The ext. analog RGB/YCrCb source in the softmix mode (see display modes)
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External OSD source

Display Modes

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Digital mode: video from the digital input
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Analog mode: video/graphics/Teletext from the analog RGB/YCrCb input
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Softmix mode: soft mixing of the video and component input
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OSD signals can be inserted digitally

Video Processing

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Full 4:4:4 processing
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RGB-to-YCrCb conversion
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Brightness, contrast, saturation for -analog component input
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Dynamic contrast improvement (DCI)
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Black level expander (BLE)
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Luma & chroma transition improvement
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Dynamic peaking
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Brightness, contrast, saturation, tint
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Programmable YCrCb-to-RGB matrix
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Programmable characteristics on R, G, B, for γ-correction, blue-stretch, white-drive
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Dithering for 8 to 6-bit digital outputs

Display Format Processing

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Prescaling of the input signal: horizontal scaling factor: 1.0 to 1/64
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Upscaling of the output signal: horizontal scaling factor: 1 to 4 (5-zone panorama generator)
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Vertical scaling factor: 0.5 to 4
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De-interlacing with line-doubling/upscaling

OSD

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Digital RGB input (6 or 12 bit/pixel)
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64 entry CLUT with 12-bit colors
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Picture frame and testpattern generation
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Half-contrast switch (0, 25%, 50%, 100%)

Display Resolutions

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640×480 (VGA; 4:3 panel)
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852×480 (W-VGA; 16:9 panel)
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800×600 (SVGA)
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1024×768 (XGA)
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1366×768 (W-XGA)

Output Interface

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2×18 or 24-bit RGB output: dual-pixel mode
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Programmable panel control signals

Miscellaneous

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Up to 2 PWM outputs
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Up to 8 general-purpose I/Os
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I2C interface (400 kHz)
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JTAG boundary scan interface
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1.8 V and 3.3 V supply
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PMQFP144 package
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