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Short description
Block diagram
Features
Tools
Short description

The Micronas Audio Delay IC MAD 4868A acts as a delay line for TV audio and -consumer audio applications. The IC is designed for synchronizing audio and video signals ensuring “Lip Sync” by delaying the audio signal with the same amount of time as the video signal is delayed in a TV’s video processing.

For TV designs, independent signals for loudspeakers, headphones and line-out or S/PDIF out must be provided, resulting in the need to delay six independent audio channels.

Especially modern flat panel TVs (LCD- or plasma-TVs) require “Lip Sync” because of their video deinterlacing, processing, scaling and pixel-oriented display.

In battery-operated “wireless TVs” using digital transmission, the compression/decompression also may delay video more than audio. Therefore, additional audio delay is necessary.

Consumer audio applications such as A/V-Receivers or HTiB can also use MAD 4868A to offer “Lip Sync” as additional feature to delay audio according to the video delay appearing in the TV, beamer or monitor used in a home cinema setup.

The MAD 4868A is equipped with all interfaces, as well as embedded RAM. This makes the IC easy to use and avoids RAM availability and pricing problems.

In its PMQFP44-1 package with 0.8 mm pitch, the MAD 4868A requires only little PCB space but is suitable for wave soldering and reflow soldering.

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Block diagram

System Architecture

With its I2S interfaces, control facilities, and RAM on a single chip, the MAD 4868A represents an easy-to-use solution. It allows simple programming of the control software, easy handling, and simple PCB design.In the functional diagram, the memory is evenly shared by three pairs of audio signals (I2S channels 1+2, 3+4, 5+6), the fourth pair (I2S channels 7+8) passes the MAD 4868A without being delayed.

Different portions of memory can be allocated for different signal pairs if the application requires this, e.g. I2S channels 1+2 and 5+6 can use ¼ of memory each, 7+8 can use ½, while 3+4 are looped through undelayed.

Functional diagram of the MAD 4868A in exemplary configuration
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Features

Delay Time and Resolution

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Total delay time of 680 ms at 48 kHz or 1020 ms at 32 kHz sampling rate
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32/18 bit word width 32-bit High-Resolution mode or 18-bit Standard mode
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Memory allocation MAD 4868A’s memory can be allocated for 1…8 audio channels. Delay time can be programmed for each channel individually.

Interfaces

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4×2-ch. standard I2S inputs and outputs allow to route eight audio channels with sampling rates of 4…192 kHz through MAD 4868A
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8-ch. Micronas I2S input and output In combination with Micronas ICs (e.g. MSP 44/46xyK, MAS 35xyH) eight audio channels can be routed through MAD 4868A by using four lines only
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I2C control for delay time programming
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Address select to set one out of two available I2C addresses

Miscellaneous

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No crystal required The MAD 4868A derives all internal clocks from the I2S clock
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Very few external components required
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5 V or 3.3 V single supply voltage
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Very low power consumption
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5 kHz to 192 kHz sampling rates
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Cascadable, extendable Two MAD 4868As can be cascaded to extend the delay time.
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Tools

Evaluation Tools

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“Visual I2C” software suite:
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I2C bus driver for PC
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Micronas “Visual I2C”
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Control application for MAD 4868A
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Evaluation Hardware:
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I2C adapter for PC parallel port
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Micronas Audio Motherboard
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“MAD 4868A / MSP 44/46xyK” application board
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