The audio decoder IC family MAS^® 35xyH represents the second generation of full-feature audio decoding ICs for consumer audio and multimedia applications. The ICs are designed for converting a compressed digital bit stream or uncompressed audio data into multiple digital output signals. All necessary processing units, together with the I/O interfaces, have been integrated in a single IC.

The MAS^® 3530H and the MAS^® 3529H are multichannel versions (5.1 Surround plus L_t/R_t downmix).

System Architecture

The DSP is designed as dedicated audio signal processor. All data input and output actions are based on a “non-cycle stealing” background DMA that does not cause any computational overhead.

The firmware implemented in the chip’s ROM provides all the decoder algorithms, the downmixing, delay line, and I/O handling, so that no download of software is necessary for operation of the MAS 35xyH.

Simplified block diagram of the MAS 35xyH

Audio Decoding

DTS Digital Theater Systems DTS 5.1 decoder

Dolby Digital (AC-3) decoder for all Dolby Digital formats from 1.0 to 5.1 channels

MPEG-1 Layer-2

Dolby Pro Logic ΙΙ Creates 5-channel surround sound from any stereo source

PCM stereo audio data

Interfaces

Two S/PDIF inputs, one S/PDIF output on chip

Two I2S inputs

Four I2S outputs Multichannel mode (eight channels on one I2S out) or standard stereo modes

I2C control for all the ICs functions and readout of information

10 general-purpose I/Os, I2C programmable

Post Processing

Spatializer N-2-2 Ultra Virtual Dolby Digital compliant virtualizer. Enables multichannel audio playback by two or three loudspeakers. The HRTF-based algorithm creates a realistic surround impression with two loudspeakers only and allows to apply for the “Virtual Dolby Digital” certification.

Bass Management “Dolby Configurations 0, 1, 2, 3”, “Multichannel Source products I, II” and “Bass to Center”

Delay lines on chip Surround: 2×25 ms, Center: 5 ms

Deemphasis for PCM and MPEG formats

Digital Volume +12 dB…−114 dB

Evaluation Support

“DMC Control” Software Suite:

I2C Driver for PC parallel port

Micronas “Visual I2C”

“DMC Control” Application

Evaluation Hardware:

I2C adapter for PC parallel port

Micronas Audio Motherboard

“Multichannel Audio” application board

Miscellaneous

Automatic format detection According to the incoming format, the de--coding algorithm is selected.

Noise Generator White noise or bandpass-shaped noise, sequencer can be programmed

S/PDIF loop-through S/PDIF input to S/PDIF output or I2S input to S/PDIF output.

On-chip clock generation, only one crystal needed for the entire application

Extra Stereo output Even during downmix operation, the IC can provide an extra Lt/Rt or Lo/Ro signal.

MAS 35xyH, Family Overview

	Decoder	MAS3529H		MAS 3530H
	DTS	−		•
	DD	•		•
	PLII	•		•
	VDD	•		•
	VDS	•		•
	MP1L2	•		•
	N-2-2 ULTRA	opt		opt

“Dolby Digital”, “Pro Logic ΙΙ”, and the double-D Symbol are trademarks of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products.

DTS, DTS Digital Surround, and DTS Virtual 5.1 are trademarks and the “DTS” Logos are registered trademarks of the Digital Theater Systems Corporation.

Spatializer^®, Spatializer N-2-2‘, and the circle-in-square device are trademarks of Desper Products, Inc.